Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-16 Freescale Semiconductor
9.4.1.5 DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)
DDR SDRAM timing configuration register 1, shown in Figure 9-6, sets the number of clock cycles
between various SDRAM control commands.
Table 9-10 describes TIMING_CFG_1 fields.
Offset 0x108 Access: Read/Write
0 1 3 4 7 8 9 11 12 1516 192021 2324 25 27 28 29 31
R
— PRETOACT ACTTOPRE — ACTTORW CASLAT REFREC — WRREC — ACTTOACT — WRTORD
W
Reset All zeros
Figure 9-6. DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)
Table 9-10. TIMING_CFG_1 Field Descriptions
Bits Name Description
0 — Reserved, should be cleared.
1–3 PRETOACT Precharge-to-activate interval (t
RP
). Determines the number of clock cycles from a precharge command
until an activate or refresh command is allowed.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
4–7 ACTTOPRE Activate to precharge interval (t
RAS
). Determines the number of clock cycles from an activate command
until a precharge command is allowed.
0000 16 clocks
0001 17 clocks
0010 18 clocks
0011 19 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
…
1111 15 clocks
8 — Reserved, should be cleared.
9–11 ACTTORW Activate to read/write interval for SDRAM (t
RCD
). Controls the number of clock cycles from an activate
command until a read or write command is allowed.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks