Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-33
9.4.1.23 Memory Data Path Read Capture ECC (CAPTURE_ECC)
The memory data path read capture ECC register, shown in Figure 9-24, stores the ECC syndrome bits that
were on the data bus when an error was detected.
Table 9-29 describes the CAPTURE_ECC fields.
9.4.1.24 Memory Error Detect (ERR_DETECT)
The memory error detect register stores the detection bits for multiple memory errors, single- and
multiple-bit ECC errors, and memory select errors. It is a read/write register. A bit can be cleared by
writing a one to the bit. System software can determine the type of memory error by examining the
contents of this register. If an error is disabled with ERR_DISABLE, the corresponding error is never
detected or captured in ERR_DETECT.
ERR_DETECT is shown in Figure 9-25.
Table 9-30 describes the ERR_DETECT fields.
Offset 0xE28 Access: Read/Write
0 31
R
ECE
W
Reset All zeros
Figure 9-24. Memory Data Path Read Capture ECC Register (CAPTURE_ECC)
Table 9-29. CAPTURE_ECC Field Descriptions
Bits Name Description
0–31 ECE Reserved
• 0–7: 8-bit ECC for first 16 bits in 16-bit bus mode; should be ignored for 32-bit
• 8–15: 8-bit ECC for second 16 bits in 16-bit bus mode; 1st 32 bits in 32-bit bus mode
• 16–23: 8-bit ECC for third 16 bits in 16-bit bus mode; should be ignored for 32-bit
• 24–31: 8-bit ECC for fourth 16 bits in 16-bit bus mode; 2nd 32 bits in 32-bit bus mode
Offset 0xE40 Access: w1c
01 23 24 25 27 28 29 30 31
RMME
—
ACE
—
MBE SBE
—
MSE
Ww1c w1c w1c w1c w1c
Reset All zeros
Figure 9-25. Memory Error Detect Register (ERR_DETECT)
Table 9-30. ERR_DETECT Field Descriptions
Bits Name Description
0 MME Multiple memory errors. This bit is cleared by software writing a 1.
0 Multiple memory errors of the same type were not detected.
1 Multiple memory errors of the same type were detected.
1–23 — Reserved