Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-35
9.4.1.26 Memory Error Interrupt Enable (ERR_INT_EN)
The memory error interrupt enable register, shown in Figure 9-27, enables ECC interrupts or memory
select error interrupts. When an enabled interrupt condition occurs, the internal int signal is asserted to the
programmable interrupt controller (PIC).
Table 9-32 describes the ERR_INT_EN fields.
30 — Reserved
31 MSED Memory select error disable
0 Memory select errors are enabled.
1 Memory select errors are disabled.
Offset 0xE48 Access: Read/Write
0 23 24 25 27 28 29 30 31
R
— ACEE — MBEE SBEE — MSEE
W
Reset All zeros
Figure 9-27. Memory Error Interrupt Enable Register (ERR_INT_EN)
Table 9-32. ERR_INT_EN Field Descriptions
Bits Name Description
0–23 — Reserved
24 ACEE Automatic calibration error interrupt enable
0 Automatic calibration errors cannot generate interrupts.
1 Automatic calibration errors generate interrupts.
25–27 — Reserved
28 MBEE Multiple-bit ECC error interrupt enable.
0 Multiple-bit ECC errors cannot generate interrupts.
1 Multiple-bit ECC errors generate interrupts.
29 SBEE Single-bit ECC error interrupt enable
0 Single-bit ECC errors cannot generate interrupts.
1 Single-bit ECC errors generate interrupts.
30 — Reserved
31 MSEE Memory select error interrupt enable
0 Memory select errors do not cause interrupts.
1 Memory select errors generate interrupts.
Table 9-31. ERR_DISABLE Field Descriptions (continued)
Bits Name Description