Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor xxxv
Figures
Figure
Number Title
Page
Number
16-115 TMR_FIPERn Register Definition ................................................................................... 16-120
16-116 TMR_ETTS1-2_H/L Register Definition......................................................................... 16-120
16-117 eTSEC-MII Connection .................................................................................................... 16-121
16-118 eTSEC-RGMII Connection............................................................................................... 16-122
16-119 Definition of Custom Preamble Sequence........................................................................ 16-129
16-120 Definition of Received Preamble Sequence...................................................................... 16-129
16-121 Ethernet Address Recognition Flowchart ......................................................................... 16-131
16-122 Location of Frame Control Blocks for TOE Parameters .................................................. 16-140
16-123 Transmit Frame Control Block ......................................................................................... 16-141
16-124 Receive Frame Control Block........................................................................................... 16-142
16-125 Structure of the Receive Queue Filer Table ...................................................................... 16-147
16-126 1588 Timer Design Partition............................................................................................. 16-158
16-127 Ethernet Sampling Points for 1588 ................................................................................... 16-158
16-128 PTP Packet Format............................................................................................................ 16-160
16-129 Buffer Format for Transmit Time-Stamp Insertion........................................................... 16-162
16-130 Transmit Frame Control Block ......................................................................................... 16-162
16-131 Example of eTSEC Memory Structure for BDs ............................................................... 16-165
16-132 Buffer Descriptor Ring...................................................................................................... 16-165
16-133 Transmit Buffer Descriptor............................................................................................... 16-166
16-134 Receive Buffer Descriptor................................................................................................. 16-169
16-135 Mapping of RxBDs to a C Data Structure ........................................................................ 16-170
17-1 I
2
C Block Diagram................................................................................................................ 17-1
17-2 I
2
C Address Register (I2CADR)........................................................................................... 17-5
17-3 I
2
C Frequency Divider Register (I2CFDR) .......................................................................... 17-5
17-4 I
2
C Control Register (I2CCR)............................................................................................... 17-6
17-5 I
2
C Status Register (I2CSR) ................................................................................................. 17-8
17-6 I
2
C Data Register (I2CDR)................................................................................................... 17-9
17-7 I
2
C Digital Filter Sampling Rate Register (I2CDFSRR).................................................... 17-10
17-8 I
2
C Interface Transaction Protocol...................................................................................... 17-11
17-9 EEPROM Contents ............................................................................................................. 17-19
17-10 EEPROM Data Format for One Register Preload Command............................................. 17-20
17-11 Example I
2
C Interrupt Service Routine Flowchart............................................................. 17-22
18-1 UART Block Diagram .......................................................................................................... 18-1
18-2 Receiver Buffer Registers (URBR1 and URBR2)................................................................ 18-5
18-3 Transmitter Holding Registers (UTHR1 and UTHR2)......................................................... 18-6
18-4 Divisor Most Significant Byte Registers (UDMB1 and UDMB2)....................................... 18-6
18-5 Divisor Least Significant Byte Registers (UDLB1 and UDLB2)......................................... 18-7
18-6 Interrupt Enable Registers (UIER1 and UIER2)................................................................... 18-8
18-7 Interrupt ID Registers (UIIR1 and UIIR2)............................................................................ 18-9
18-8 FIFO Control Registers (UFCR1 and UFCR2)................................................................... 18-10
18-9 Line Control Register (ULCR1 and ULCR2)..................................................................... 18-11