Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-43
If a transaction request is issued to the DDR memory controller and the address does not lie within any of
the programmed address ranges for an enabled chip select, a memory select error is flagged. Errors are
described in detail in Section 9.5.12, “Error Management.”
Using a memory-polling algorithm at power-on reset or by querying the JEDEC serial presence detect
capability of memory modules, system firmware uses the memory-boundary registers to configure the
DDR memory controller to map the size of each bank in memory. The memory controller uses its bank
map to assert the appropriate MCSn signal for memory accesses according to the provided bank starting
and ending addresses. The memory banks are not required to be mapped to a contiguous address space.
9.5.2 DDR SDRAM Address Multiplexing
The following tables (Table 9-38 and Table 9-39) show the address bit encodings for each DDR SDRAM
configuration. The address presented at the memory controller signals MA[13:0] use MA[13] as the msb
and MA[0] as the lsb. Also, MA[10] is used as the auto-precharge bit in DDR2 modes for reads and writes,
so the column address can never use MA[10].
Table 9-37. Supported DDR2 SDRAM Device Configurations
SDRAM Device Device Configuration
Row  Column 
Bank Bits
32-Bit Bank Size Two Banks of Memory
256 Mbits 32 Mbits  8 13  10  2 128 Mbytes 256 Mbytes
256 Mbits 16 Mbits  16 13  9  2 64 Mbytes 128 Mbytes
512 Mbits 64 Mbits  8 14  10  2 256 Mbytes 512 Mbytes
512 Mbits 32 Mbits  16 13  10  2 128 Mbytes 256 Mbytes
1 Gbits 128 Mbits  8 14  10  3 512 Mbytes 1 Gbyte
1 Gbits 64 Mbits  16 13  10  3 256 Mbytes 512 Mbytes
2 Gbits 128 Mbits  16 14  10  3 512 Mbytes 1 Gbytes
Table 9-38. DDR2 Address Multiplexing for 32-Bit Data Bus with Interleaving and Partial Array Self Refresh
Disabled
Row
¥
Col
msb Address from Core Master lsb
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30–31
14 
10  3
MRAS
131211109876543210
MBA 210
MCAS 9876543210
14 
10  2
MRAS 131211109876543210
MBA 10
MCAS 9876543210
13 
10  3
MRAS 1211109876543210
MBA 210
MCAS 9876543210