Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-47
9.5.4 DDR SDRAM Interface Timing
The DDR memory controller supports four-beat bursts to SDRAM. For single-beat reads, the DDR
memory controller performs a four-beat burst read, but ignores the last three beats. Single-beat writes are
performed by masking the last three beats of the four-beat burst using the data mask MDM[0:3]. If ECC
is disabled, writes smaller than double words are performed by appropriately activating the data mask. If
ECC is enabled, the controller performs a read-modify write.
NOTE
If a second read or write is pending, reads shorter than four beats are not
terminated early even if some data is irrelevant.
To accommodate available memory technologies across a wide spectrum of operating frequencies, the
DDR memory controller allows the setting of the intervals defined in Table 9-42 with granularity of one
memory clock cycle, except for CASLAT, which can be programmed with 1/2 clock granularity.
Read H H L H L H Logical bank select L Column
Read with
auto-precharge
H H L H L H Logical bank select H Column
Write H H L H L L Logical bank select L Column
Write with
auto-precharge
H H L H L L Logical bank select H Column
Mode register set H H L L L L Opcode Opcode Opcode and mode
Auto refresh H H L L L H X X X
Self refresh H L L L L H X X X
Table 9-42. DDR SDRAM Interface Timing Intervals
Timing Intervals Definition
ACTTOACT The number of clock cycles from a bank-activate command until another bank-activate command within
a physical bank. This interval is listed in the AC specifications of the SDRAM as t
RRD
.
ACTTOPRE The number of clock cycles from an activate command until a precharge command is allowed. This
interval is listed in the AC specifications of the SDRAM as t
RAS
.
ACTTORW The number of clock cycles from an activate command until a read or write command is allowed. This
interval is listed in the AC specifications of the SDRAM as t
RCD
.
BSTOPRE The number of clock cycles to maintain a page open after an access. The page open duration counter
is reloaded with BSTOPRE each time the page is accessed (including page hits). When the counter
expires, the open page is closed with an SDRAM precharge bank command as soon as possible.
CASLAT Used in conjunction with additive latency to obtain the READ latency. The number of clock cycles
between the registration of a READ command by the SDRAM and the availability of the first piece of
output data. If a READ command is registered at clock edge n, and the read latency is m clocks, the data
is available nominally coincident with clock edge n + m.
Table 9-41. DDR SDRAM Command Table (continued)
Operation
CKE
Prev.
CKE
Current
MCS MRAS MCAS MWE MBA MA10 MA