Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-58 Freescale Semiconductor
in systems which use many different channels. Page mode is disabled by clearing
DDR_SDRAM_INTERVAL[BSTOPRE] or setting CSn_CONFIG[AP_nEN].
9.5.11 Error Checking and Correcting (ECC)
The DDR memory controller supports error checking and correcting (ECC) for the data path between the
core master and system memory. The memory detects all double-bit errors, detects all multi-bit errors
within a nibble, and corrects all single-bit errors. Other errors may be detected, but are not guaranteed to
be corrected or detected. Multiple-bit errors are always reported when error reporting is enabled. When a
single-bit error occurs, the single-bit error counter register is incremented, and its value compared to the
single-bit error trigger register. An error is reported when these values are equal. The single-bit error
registers can be programmed such that minor memory faults are corrected and ignored, but a catastrophic
memory failure generates an interrupt.
For writes that are smaller than 64 bits, the DDR memory controller performs a double-word read from
system memory of the address for the write (checking for errors), and merges the write data with the data
read from memory. Then, a new ECC code is generated for the merged double word. The data and ECC
code is then written to memory. If a multi-bit error is detected on the read, the transaction completes the
read-modify-write to keep the DDR memory controller from hanging. However, the corrupt data is masked
on the write, so the original contents in SDRAM remain unchanged.
The syndrome encodings for the ECC code are shown in Table 9-45 and Table 9-46.
In 32-bit mode, Table 9-45 is split into 2 halves. The first half, consisting of rows 0–31, is used to calculate
the ECC bits for the first 32 data bits of any 64-bit granule of data. This always applies to the odd data
beats on the DDR data bus. The second half of the table, consisting of rows 32–63, is used to calculate the
ECC bits for the second 32 bits of any 64-bit granule of data. This always applies to the even data beats
on the DDR data bus.
Table 9-45. DDR SDRAM ECC Syndrome Encoding
Data
Bit
Syndrome Bit
Data
Bit
Syndrome Bit
01234567 01234567
0
•• •
32
•• •
1
•• •
33
•• •
2
•• •
34
•••
3
•••
35
•• •
4
•• •
36
•• •
5
•• •
37
•••
6
•••
38
•••••
7
•••
39
•• •• •
8
•• •
40
•• •
9
•• •
41
•••
10
•••
42
•••••
11
•••
43
•••••