Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-61
At system reset, initialization software (boot code) must set up the programmable parameters in the
memory interface configuration registers. See Section 9.4.1, “Register Descriptions,” for more detailed
descriptions of the configuration registers. These parameters are shown in Table 9-48.
Table 9-48. Memory Interface Configuration Register Initialization Parameters
Name Description Parameter Section/page
CSn_BNDS Chip select memory bounds SAn
EAn
9.4.1.1/9-10
CSn_CONFIG Chip select configuration CS_n_EN
AP_n_EN
ODT_RD_CFG
ODT_WR_CFG
BA_BITS_CS_n
ROW_BITS_CS_n
COL_BITS_CS_n
9.4.1.2/9-11
TIMING_CFG_3 Extended timing parameters for fields
in TIMING_CFG_1
EXT_REFREC 9.4.1.3/9-13
TIMING_CFG_0 Timing configuration RWT
WRT
RRT
WWT
ACT_PD_EXIT
PRE_PD_EXIT
ODT_PD_EXIT
MRS_CYC
9.4.1.4/9-14
TIMING_CFG_1 Timing configuration PRETOACT
ACTTOPRE
ACTTORW
CASLAT
REFREC
WRREC
ACTTOACT
WRTORD
9.4.1.5/9-16
TIMING_CFG_2 Timing configuration ADD_LAT
CPO
WR_LAT
RD_TO_PRE
WR_DATA_DELAY
CKE_PLS
FOUR_ACT
9.4.1.6/9-18
DDR_SDRAM_CFG Control configuration SREN
ECC_EN
RD_EN
SDRAM_TYPE
DYN_PWR
DBW
NCAP
2T_EN
BA_INTLV_CTL
HSE
BI
9.4.1.7/9-19
DDR_SDRAM_CFG_2 Control configuration DLL_RST_DIS
DQS_CFG
ODT_CFG
NUM_PR
D_INIT
9.4.1.8/9-22
DDR_SDRAM_MODE Mode configuration ESDMODE
SDMODE
9.4.1.9/9-23
DDR_SDRAM_MODE_2 Mode configuration ESDMODE2
ESDMODE3
9.4.1.10/9-24
DDR_SDRAM_INTERVAL Interval configuration REFINT
BSTOPRE
9.4.1.12/9-27
DDR_DATA_INIT Data initialization configuration
register
INIT_VALUE 9.4.1.13/9-28
DDR_SDRAM_CLK_CNTL Clock adjust CLK_ADJUST 9.4.1.14/9-28
DDR_INIT_ADDR Initialization address INIT_ADDR 9.4.1.15/9-29