Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-1
Chapter 10
Enhanced Local Bus Controller
This chapter describes the enhanced local bus controller (eLBC) block. It describes the external signals
and the memory-mapped registers as well as a functional description of the general-purpose chip-select
machine (GPCM), NAND Flash control machine (FCM), and user-programmable machines (UPMs) of the
eLBC. Finally, it includes an initialization and applications information section with many specific
examples of its use.
10.1 Introduction
Figure 10-1 is a functional block diagram of the eLBC, which supports three interfaces: GPCM, FCM, and
UPM controllers.
Figure 10-1. Enhanced Local Bus Controller Block Diagram
UPM
CTRL
GPCM
Memory
Controller
Address and
Data Machine
Banks and
Config
Regs
UPM
RAM
Transfer Acknowledge
Local Address
Local Data
Refresh
Timers/
Counters
Local
Memory
Compare
Control Signal Timing
Generator
GPCM CTRL
LOE
LGTA
LBCTL
UPM CTRL
LGPL[0:3]
LGPL4/LUPWAIT
LGPL5
Clock
Divider
Interface
and Mux
Addr/Data
Mux
FCM
CTRL
FCM
RAM
FCM CTRL
LFCLE
LFALE
LFWE
0
LFRE
LFWP
LFRB
LCS[0:3]
LWE
[0:1]
LD[0:15]
LBS
[0:1]
LCLK0
LDVAL
LSRCID[0:4]
LA[0:25]