Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-15
Table 10-8 describes ORn fields for FCM mode.
Table 10-8. ORn—FCM Field Descriptions
Bits Name Description
0–16 AM FCM address mask. Masks corresponding BRn bits. Masking address bits independently allows external
devices of different size address ranges to be used. Address mask bits can be set or cleared in any order
in the field, allowing a resource to reside in more than one area of the address map.
0 Corresponding address bits are masked.
1 Corresponding address bits are used in the comparison between base and transaction addresses.
17–18 — Reserved
19 BCTLD Buffer control disable. Disables assertion of LBCTL during access to the current memory bank.
0 LBCTL is asserted upon access to the current memory bank.
1 LBCTL is not asserted upon access to the current memory bank.
20 — Reserved
21 PGS NAND Flash EEPROM page size, buffer size, and block size.
0 Page size of 512 main area bytes plus 16 spare area bytes (small page devices);
FCM RAM buffers are 1 Kbyte each; Flash block size of 16 Kbytes.
1 Page size of 2048 main area bytes plus 64 spare area bytes (large page devices);
FCM RAM buffers are 4 Kbytes each; Flash block size of 128 Kbytes.
22 CSCT Chip select to command time. Determines how far in advance LCS
n is asserted prior to any bus activity
during a NAND Flash access handled by the FCM. This helps meet chip-select setup times for slow
memories.
TRLX CSCT Meaning
0 0 The chip-select is asserted 1 clock cycle before any command.
0 1 The chip-select is asserted 4 clock cycles before any command.
1 0 The chip-select is asserted 2 clock cycles before any command.
1 1 The chip-select is asserted 8 clock cycles before any command.
23 CST Command setup time. Determines the delay of LFWE0
assertion relative to the command, address, or data
change when the external memory access is handled by the FCM.
TRLX CST Meaning
0 0 The write-enable is asserted coincident with any command.
0 1 The write-enable is asserted 0.25 clock cycles after any command, address, or
data.
1 0 The write-enable is asserted 0.5 clock cycles after any command, address, or
data.
1 1 The write-enable is asserted 1 clock cycle after any command, address, or data.