Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-17
10.3.1.2.4 Option Registers (ORn)—UPM Mode
Figure 10-5 shows the bit fields for ORn when the corresponding BRn[MSEL] selects a UPM machine.
Table 10-9 describes BRn fields for UPM mode.
30 EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a read
access from the current bank and the next access.
TRLX EHTR Meaning
0 0 1 idle clock cycle is inserted.
0 1 2 idle clock cycles are inserted.
1 0 4 idle clock cycles are inserted.
1 1 8 idle clock cycles are inserted.
31 — Reserved
Offset OR0: 0x0_5004
OR1: 0x0_500c
OR2: 0x0_5014
OR3: 0x0_501c
Access: Read/Write
0 15
R
AM
W
Reset All zeros
16 17 18 19 20 22 23 24 28 29 30 31
R
AM — BCTLD — BI —
TRLX
EHTR —
W
Reset All zeros
1
Refer to Table 10-5 for the OR0 reset value. All other option registers have all bits cleared.
Figure 10-5. Option Registers (ORn) in UPM Mode
Table 10-9. ORn—UPM Field Descriptions
Bits Name Description
0–16 AM UPM address mask. Masks corresponding BRn bits. Masking address bits independently allows external
devices of different size address ranges to be used. Address mask bits can be set or cleared in any order in
the field, allowing a resource to reside in more than one area of the address map.
0 Corresponding address bits are masked.
1 The corresponding address bits are used in the comparison with address pins.
17–18 — Reserved
Table 10-8. ORn—FCM Field Descriptions (continued)
Bits Name Description