Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-35
Table 10-25 describes FIR fields.
10.3.1.19 Flash Command Register (FCR)
The local bus Flash command register (FCR), shown in Figure 10-23, holds up to four NAND Flash
EEPROM command bytes that may be referenced by opcodes in FIR during FCM operation. The values
of the commands should follow the manufacturer’s datasheet for the relevant NAND Flash device.
Table 10-26 describes FCR fields.
Table 10-25. FIR Field Descriptions
Bits Name Description
0–3 OP0 FCM operation codes. OP0 is executed first, followed by OP1, through to OP7.
0000 NOP—No-operation and end of operation sequence
0001 CA—Issue current column address as set in FPAR, with length set by ORx[PGS]
0010 PA—Issue current block+page address as set in FBAR and FPAR, with length set by FMR[AL]
0011 UA—Issue user-defined address byte from next AS field in MDR
0100 CM0—Issue command from FCR[CMD0]
0101 CM1—Issue command from FCR[CMD1]
0110 CM2—Issue command from FCR[CMD2]
0111 CM3—Issue command from FCR[CMD3]
1000 WB—Write FBCR bytes of data from current FCM buffer to Flash device
1001 WS—Write one byte (8b port) of data from next AS field of MDR to Flash device
1010 RB—Read FBCR bytes of data from Flash device into current FCM RAM buffer
1011 RS—Read one byte (8b port) of data from Flash device into next AS field of MDR
1100 CW0—Wait for LFRB
to return high or time-out, then issue command from FCR[CMD0]
1101 CW1—Wait for LFRB
to return high or time-out, then issue command from FCR[CMD1]
1110 RBW—Wait for LFRB to return high or time-out, then read FBCR bytes of data from Flash device
into current FCM RAM buffer
1111 RSW—Wait for LFRB
to return high or time-out, then read one byte (8b port) of data from Flash
device into next AS field of MDR
4–7 OP1
8–11 OP2
12–15 OP3
16–19 OP4
20–23 OP5
24–27 OP6
28–31 OP7
Offset 0x0_50E8 Access: Read/Write
0781516232431
R
CMD0 CMD1 CMD2 CMD3
W
Reset All zeros
Figure 10-23. Flash Command Register
Table 10-26. FCR Field Descriptions
Bits Name Description
0–7 CMD0 General purpose FCM Flash command byte 0. Opcodes in FIR that issue command index 0 write
CMD0 to the NAND Flash command/data bus.
8–15 CMD1 General purpose FCM Flash command byte 1. Opcodes in FIR that issue command index 1 write
CMD1 to the NAND Flash command/data bus.
16–23 CMD2 General purpose FCM Flash command byte 2. Opcodes in FIR that issue command index 2 write
CMD2 to the NAND Flash command/data bus.
24–31 CMD3 General purpose FCM Flash command byte 3. Opcodes in FIR that issue command index 3 write
CMD3 to the NAND Flash command/data bus.