Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-74 Freescale Semiconductor
Figure 10-62. UPM Clock Scheme for LCRR[CLKDIV] = 4 or 8
10.4.4.4 RAM Array
The RAM array for each UPM is 64 locations deep and 32 bits wide, as shown in Figure 10-63. The signals
at the bottom of the figure are UPM outputs. The selected LCS
n is for the bank that matches the current
address. The selected LBS is for the byte lanes read or written by the access.
Figure 10-63. RAM Array and Signal Generation
10.4.4.4.1 RAM Words
The RAM word is a 32-bit microinstruction stored in one of 64 locations in the RAM array. It specifies
timing for external signals controlled by the UPM. Figure 10-64 shows the RAM word fields. When
LCRR[CLKDIV] = 4 or 8, the CSTn and BSTn bits determine the state of UPM signals LCS
n and
LBS
[0:1] at each quarter phase of the bus clock. When LCRR[CLKDIV] = 2, CST2 and CST4 are ignored
and the external has the values defined by CST1 and CST3 but extended to half the clock cycle in duration.
The same interpretation occurs for the BSTn bits when LCRR[CLKDIV] = 2.
LCLK
T1
T2
T3
T4
T1, T2, T3, T4
LGPL0 LGPL2 LGPL3 LGPL4 LGPL5
External Signals Timing Generator
RAM Array
CS Line
Selector
Byte Select
Logic
Current Bank
32 Bits
64 deep
LGPL1
Clock Phases
LBS[0:1]
LCS
[0:3]
BRn[PS], LA[24:25]