Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-86 Freescale Semiconductor
10.5.3 Command Sequence Examples for NAND Flash EEPROM
In order to program the eLBC and FCM for executing NAND Flash command sequences, command codes
and pause states should be obtained from the relevant NAND Flash device data sheet and programmed into
FCM configuration registers. This section illustrates some common sequences for large-page,
multi-gigabit NAND Flash EEPROMs; however, details should be verified against manufacturers’
specific programming data.
Throughout these examples it is assumed that one or more banks of eLBC has been configured under FCM
control (BRn[MSEL] = 001), with base address, port size, ECC mode, and timing parameters configured
in accordance with the device’s hardware specifications.
10.5.3.1 NAND Flash Soft Reset Command Sequence Example
An example of configuring FCM to execute a soft reset command to large-page NAND Flash is shown in
Table 10-44. This sequence does not require use of the shared FCM buffer RAM. The sequence is initiated
by writing FMR[OP] = 10, and issuing a special operation to the bank. At the conclusion of the sequence,
eLBC will issue a command complete interrupt (LTESR[CC]) if interrupts are enabled.
Half Word 000 OP0 OP1 OP0
001 — OP1 OP1
010 OP2 OP3 OP2
100 OP4 OP5 OP4
101 — OP5 OP5
110 OP6 OP7 OP6
Word 000 OP0 OP1 OP0
100 OP4 OP5 OP4
1
Address state is the calculated address for port size.
Table 10-44. FCM Register Settings for Soft Reset (ORn[PGS] = 1)
Register Initial Contents Description
FCR 0xFF000000 CMD0 = 0xFF = reset command; other commands unused
FBAR — unused
FPAR — unused
FBCR — unused
Table 10-43. Data Bus Drive Requirements For Read Cycles (continued)
Transfer
Size
Address
State
1
3 lsbs
Port Size/LD Data Bus Assignments
16-Bit 8-Bit
0–7 8–15 16–23 24–31 0–7 8–15 16–23 24–31