Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-25
be cleared with a single register write. For a card interrupt (IRQSTAT[CINT]), the card must stop asserting
the interrupt before writing one to clear. Otherwise, the CINT bit is set again.
Figure 11-12 shows the interrupt status register.
Table 11-14 describes the IRQSTAT fields.
Offset: 0x030 (IRQSTAT) Access: w1c
0 2 3 4 6 7 8 9 10 11 12 13 14 15
R
—
DMAE
—
AC12E
—
DEBE DCE DTOE CIE CEBE CCE CTOE
W w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset All zeros
16 22 23 24 25 26 27 28 29 30 31
R
—
CINT CRM CINS BRR BWR DINT BGE TC CC
W w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset All zeros
Figure 11-12. Interrupt Status Register (IRQSTAT)
Table 11-14. IRQSTAT Field Descriptions
Bit Name Description
0–2 — Reserved
3 DMAE DMA error. Occurs when internal DMA transfer failed. This bit is set when some error occurs in the
data transfer. The value in the DMA system address register is the next fetch address where the error
occurs. Since any error corrupts the entire data block, the host driver should restart the transfer from
the corrupted block boundary. The address of the block boundary can be calculated from the current
DS_ADDR value or the remaining number of blocks and the block size.
0No Error
1Error
4–6 — Reserved
7 AC12E Auto CMD12 error. Occurs when one of the bits in AUTOC12ERR is set. This bit is also set when Auto
CMD12 is not executed due to a previous command error.
0No Error
1Error
8—Reserved
9 DEBE Data end bit error. Occurs when detecting 0 at the end bit position of read data on the SD_DAT line or
at the end bit position of the CRC.
0No Error
1Error
Note: When DEBE and CINT are set, the software should ignore DEBE. But, it must not ignore the
other status bits. The software should also clear this bit by writing 1 to it. It is highly
recommended to clear this bit before the next transfer.