Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-27
24 CRM Card removal. This bit is set if PRSSTAT[CINS] changes from 1 to 0. When the host driver writes 1 to
this bit to clear it, the status of PRSSTAT[CINS] should be confirmed. Because the card-detect state
may be changed when the host driver clears this bit, an interrupt event may not be generated.
When this bit is cleared, it is set again if no card is inserted. To leave it cleared, clear
IRQSTATEN[CRMSEN].
0 Card state unstable or inserted
1 Card removed
25 CINS Card insertion. This bit is set if PRSSTAT[CINS] changes from 0 to 1. When the host driver writes 1 to
this bit to clear it, the status of PRSSTAT[CINS] should be confirmed. Because the card-detect state
may be changed when the host driver clears this bit, an interrupt event may not be generated.
When this bit is cleared, it is set again if a card has been inserted. To leave it cleared, clear
IRQSTATEN[CINSEN].
0 Card state unstable or removed
1 Card inserted
26 BRR Buffer read ready. This bit is set if PRSSTAT[BREN] changes from 0 to 1.
0 Not ready to read buffer
1 Ready to read buffer
27 BWR Buffer write ready. This bit is set if PRSSTAT[BWEN] changes from 0 to 1.
0 Not ready to write buffer
1 Ready to write buffer
28 DINT DMA interrupt. Occurs when the internal DMA finishes the data transfer successfully. If errors occur
during data transfer, this bit is not set. Instead, the DMAE bit is set.
0 No DMA interrupt
1 DMA interrupt is generated
29 BGE Block gap event. If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction is
stopped at a block gap. If PROCTL[SABGREQ] is cleared, this bit is not set.
During a read transaction, this bit is set at the falling edge of the SD_DAT line active status (when the
transaction is stopped at SD bus timing). Read wait must be supported to use this function.
During a write transaction, this bit is set at the falling edge of PRSSTAT[WTA] (after reading the CRC
status at SD bus timing).
0 No block gap event
1 Transaction stopped at block gap
30 TC Transfer complete. This bit is set when a read or write transfer is completed.
For a read transaction, this bit is set at the falling edge of PRSSTAT[WTA]. There are two cases in
which this interrupt is generated:
• When a data transfer is completed, as specified by data length (after the last data has been read to
the host system).
• When data has stopped at the block gap and completed the data transfer by setting
PROCTL[SABGREQ] (after valid data has been read to the host system).
For a write transaction, this bit is set at the falling edge of PRSSTAT[DLA]. There are two cases in
which this interrupt is generated:
• When the last data is written to the SD card, as specified by data length and the busy signal is
released.
• When data transfers are stopped at the block gap by setting PROCTL[SABGREQ] and data
transfers have completed (after valid data is written to the SD card and the busy signal is released).
31 CC Command complete. This bit is set when the end bit of the command response is received (except Auto
CMD12). Refer to PRSSTAT[CIHB].
0 No command complete
1 Command complete
Table 11-14. IRQSTAT Field Descriptions (continued)
Bit Name Description