Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-32 Freescale Semiconductor
12 CIEIEN Command index error interrupt enable
0Masked
1 Enabled
13 CEBEIEN Command end bit error interrupt enable
0Masked
1 Enabled
14 CCEIEN Command CRC error interrupt enable
0Masked
1 Enabled
15 CTOEIEN Command timeout error interrupt enable
0Masked
1 Enabled
16–22 — Reserved
23 CINTIEN Card interrupt signal enable
0Masked
1 Enabled
24 CRMIEN Card removal interrupt enable
0Masked
1 Enabled
25 CINSIEN Card insertion interrupt enable
0Masked
1 Enabled
26 BRRIEN Buffer read ready interrupt enable
0Masked
1 Enabled
27 BWRIEN Buffer write ready interrupt enable
0Masked
1 Enabled
28 DINTIEN DMA interrupt enable
0Masked
1 Enabled
29 BGEIEN Block gap event interrupt enable
0Masked
1 Enabled
30 TCIEN Transfer complete interrupt enable
0Masked
1 Enabled
31 CCIEN Command complete interrupt enable
0Masked
1 Enabled
Table 11-19. IRQSIGEN Field Descriptions (continued)
Bit Name Description