Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-46 Freescale Semiconductor
• Figure 11-25 (b) for the sequences of software and hardware events that take place during card
interrupt handling procedure
Figure 11-25. a) Card Interrupt Scheme; b) Card Interrupt Detection and Handling Procedure
11.5.7 Card Insertion and Removal Detection
The eSDHC uses the SD_DAT[3] pin or the SD_CD pin to detect card insertion or removal. When
SD_DAT[3] pin is used for card detection, user needs to pull-down this pad as a default state. When there
is no card on the MMC/SD bus, the SD_DAT[3] is pulled to a low voltage level by default. When any card
is inserted to or removed from the socket, the eSDHC detects the logic value changes on the SD_DAT[3]
pin and generates an interrupt.
When SD_DAT[3] pin is not used for card detection, SD_CD
must be connected for card detection. It may
be implemented by a GPIO. Whether SD_DAT[3] is configured for card detection or not, SD_CD
is
always a reference for card detection, either SD_DAT[3] or SD_CD reports card inserted, the eSDHC
informs the host system that a card is inserted, and the interrupt is sent if it is enabled.
11.5.8 Power Management
When there is no operation between eSDHC and the card through SD bus, the internal clocks in the chip
level clock control module can be completely disabled to save power. When eSDHC is needed to
SDIO Interrupt Status
SDIO Interrupt Enable
eSDHC Registers
Command/
Response
Handling
IRQ Detecting & Steering
SD Host
SDIO Card
SDIO Card
IRQ Routing
IRQ0 IRQ1
Function 0 Function 1
Clear
IRQ1
Clear
IRQ0
Register Bus IRQ to CPU
Detect & Steer Card IRQ
Read IRQ Status Register
Disable Card IRQ in Host
Interrogate & Service Card IRQ
Enable Card IRQ in Host
Start
Response Error
?
Clear Card IRQ in Card
Enable Card IRQ in Host
End
Ye s
No
b)a)