Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor lv
Tables
Table
Number Title
Page
Number
18-4 URBR Field Descriptions ..................................................................................................... 18-5
18-5 UTHR Field Descriptions ..................................................................................................... 18-6
18-6 UDMB Field Descriptions .................................................................................................... 18-6
18-7 UDLB Field Descriptions ..................................................................................................... 18-7
18-8 Baud Rate Examples ............................................................................................................. 18-7
18-9 UIER Field Descriptions....................................................................................................... 18-8
18-10 UIIR Field Descriptions........................................................................................................ 18-9
18-11 UIIR IID Bits Summary........................................................................................................ 18-9
18-12 UFCR Field Descriptions.................................................................................................... 18-10
18-13 ULCR Field Descriptions.................................................................................................... 18-11
18-14 Parity Selection Using ULCR[PEN], ULCR[SP], and ULCR[EPS].................................. 18-12
18-15 UMCR Field Descriptions .................................................................................................. 18-12
18-16 ULSR Field Descriptions.................................................................................................... 18-13
18-17 USCR Field Descriptions.................................................................................................... 18-14
18-18 UAFR Field Descriptions.................................................................................................... 18-15
18-19 UDSR Field Descriptions.................................................................................................... 18-15
18-20 UDSR[TXRDY] Set Conditions......................................................................................... 18-16
18-21 UDSR[TXRDY] Cleared Conditions.................................................................................. 18-16
18-22 UDSR[RXRDY] Set Conditions......................................................................................... 18-16
18-23 UDSR[RXRDY] Cleared.................................................................................................... 18-16
19-1 Signal Properties ................................................................................................................... 19-6
19-2 Detailed Signal Descriptions................................................................................................. 19-6
19-3 SPI Register Summary.......................................................................................................... 19-8
19-4 SPMODE Field Descriptions................................................................................................ 19-8
19-5 SPIE Field Descriptions...................................................................................................... 19-11
19-6 SPIM Field Descriptions..................................................................................................... 19-12
19-7 SPCOM Field Descriptions................................................................................................. 19-13
19-8 SPI Transmit Data Hold Field Descriptions........................................................................ 19-13
19-9 SPI Receive Data Hold Field Descriptions......................................................................... 19-14
20-1 JTAG Test Signals Summary ................................................................................................ 20-2
20-2 JTAG Test—Detailed Signal Descriptions............................................................................ 20-2
21-1 GPIO—Signal Descriptions.................................................................................................. 21-2
21-2 GPIO Register Address Map................................................................................................. 21-2
21-3 GPDIR Bit Settings............................................................................................................... 21-3
21-4 GPODR Bit Settings ............................................................................................................. 21-3
21-5 GPnDAT Bit Settings............................................................................................................ 21-4
21-6 GPIER Bit Settings ............................................................................................................... 21-4
21-7 GPIMR Bit Settings .............................................................................................................. 21-5
21-8 GPICR Bit Settings ............................................................................................................... 21-5
A-1 Local Access Register Memory Map..................................................................................... A-1
A-2 System Configuration Registers............................................................................................. A-2