Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 12-15
See Table 12-13 for the DMAGPOR definition.
12.3.11 DMA Channel n Priority (DCHPRIn), n = 0–15
When the fixed-priority channel arbitration mode is enabled (DMACR[ERCA] = 0), the contents of these
registers define the unique priorities associated with each channel within the group. The channel priorities
are evaluated by numeric value, that is, 0 is the lowest priority, 1 is the next higher priority, then 2, 3, and
so on. Software must program the channel priorities with unique values, otherwise a configuration error is
reported. The range of the priority value is limited to the values of 0 through 15. When read, the GRPPRI
bits of the DCHPRI register reflect the current priority level of the channels. See Figure 12-2 and
Table 12-2 for the DMACR definition.
Channel preemption is enabled on a per channel basis by setting the ECP bit in the DCHPRI register.
Channel preemption allows the executing channel’s data transfers to be temporarily suspended in favor of
starting a higher priority channel. Once the preempting channel has completed all of its minor loop data
transfers, the preempted channel is restored and resumes execution. After the restored channel completes
one read/write sequence, it is again eligible for preemption. If any higher priority channel is requesting
service, the restored channel is suspended and the higher priority channel is serviced. Nested preemption
(attempting to preempt a preempting channel) is not supported. Once a preempting channel begins
execution, it cannot be preempted. Preemption is only available when fixed arbitration is selected for
channel arbitration modes.
Table 12-13. DMAGPOR Field Descriptions
Bits Name Description
31–13 — Reserved
12 DMA_PRIORITY DMA priority.
0Low priority
1 High priority
11–7 — Reserved
6 SNOOP_ENABLE Snoop attribute.
0 DMA transactions are not snooped by e300 CPU data cache
1 DMA transactions are snooped by e300 CPU data cache
5—Reserved
4 ERROR_DISABLE Ignore or react to bus errors.
0 React to bus transaction errors
1 Ignore bus transaction errors
3—Reserved
2 RD_SAFE_
ENABLE
Read Safe enable. This bit should be set only if the target of read dma operation is a well
behaved memory which is not affected by the read operation and returns the same data if read
again from the same location. This means that unaligned reading operation can be rounded up
to enable more efficient read operations.
0 It is not safe to read more bytes that were intended
1 It is safe to read more bytes that were intended
1–0 — Reserved