Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
12-26 Freescale Semiconductor
minimize the time needed to fetch the activated channel’s descriptor and load it into the DMA engine
addr_path.channel_{x,y} registers.
Figure 12-23. DMA Operation—Part 1
In the second part of the basic data flow as shown in Figure 12-24, the modules associated with the data
transfer (addr_path, data_path and control) sequence through the required source reads and destination
writes to perform the actual data movement. The source reads are initiated and the fetched data is
temporarily stored in the data_path module until it is gated onto the AHB bus during the destination write.
dma_ipi_int[n – 1:0]
Register Interface
DMA
AHB Interface
data_path controladdr_path
wdata[31:0]
addr
rdata[31:0]
SRAM Transfer Control
Descriptor
(TCD)
DMA Engine
0
j
j+1
n–1
pmodel_charb