Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
12-28 Freescale Semiconductor
descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in
Figure 12-25.
Figure 12-25. DMA Operation—Part 3
12.5 Initialization/Application Information
This section discusses the DMA initialization and programming errors.
12.5.1 DMA Initialization
The following sequence is a typical initialization of the DMA.
1. Write the DMACR register if a configuration other than the default is desired.
2. Write the channel priority levels into the DCHPRIn registers if a configuration other than the
default is desired.
3. Enable error interrupts in the DMAEEI registers if so desired.
4. Write the 32 bytes TCD for each channel that may request service.
5. Request channel service by software (setting the
TCD.start bit).
Once any channel requests service, a channel is selected for execution based on the arbitration and priority
levels written into the programmer's model. The DMA engine reads the entire TCD for the selected
dma_ipi_int[n – 1:0]
Register Interface
DMA
AHB Interface
data_path controladdr_path
pmodel_charb
wdata[31:0]
addr
rdata[31:0]
SRAM Transfer Control
Descriptor
(TCD)
DMA Engine
0
j
j + 1
n – 1