Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
lviii Freescale Semiconductor
their functions. In addition, the interrupt configuration, control, and status registers are described
in this chapter.
• Chapter 9, “DDR Memory Controller,” describes the DDR2 memory controller of the device. This
fully programmable controller supports most DDR memories available today, including both
buffered and unbuffered devices. Dynamic power management and auto-precharge modes simplify
memory system design.
• Chapter 10, “Enhanced Local Bus Controller,” describes the enhanced local bus controller (eLBC)
of the device. It describes the external signals and the memory-mapped registers as well as a
functional description of the general-purpose chip-select machine (GPCM), Flash control machine
(FCM), and user-programmable machines (UPMs) of the eLBC. Also, it includes an initialization
and applications information section with many specific examples of its use.
• Chapter 11, “Enhanced Secure Digital Host Controller,” describes the enhanced SD Host
Controller, which provides an interface between the host system and SD/MMC/SDIO cards. It
provides a functional description of the major system blocks and includes command information
for the host.
• Chapter 12, “DMA Controller (DMAC),” describes a second-generation platform module capable
of performing complex data transfers with minimal intervention from a host processor using n
programmable channels. It is intended for use in applications where the data size to be transferred
is statically known, and is not defined within the data packet itself. The DMA hardware supports
single design with two channels (Tx and Rx), 32-byte transfer control descriptor per channel stored
in local memory, and 32 bytes of data registers, used as temporary storage to support burst
transfers.
• Chapter 13, “Universal Serial Bus Interface,” describes the universal serial bus (USB) interface.
The USB DR module is a USB 2.0-compliant serial interface engine for implementing a USB
interface. The DR module supports the required signaling for UTMI low pin count interface
(ULPI) transceivers (PHYs). An external PHY would be used to interface to ULPI.
• Chapter 14, “PCI Express Interface Controller,” describes the PCI Express interface controller,
which connects the CSB to the PCI Express bus, a 2.5 GHz serial interface that supports up to a x2
lane. As both a master (initiator) and a target device, the PCI Express interface is capable of high
bandwidth data transfer and is designed to support the next generation I/O devices.
• Chapter 15, “SerDes PHY,” describes the block which includes the serializer/deserializer PHY, the
protocol converter per protocol, the protocol mux, and the control registers and control logic. It
supports x1 PCI Express.
• Chapter 16, “Enhanced Three-Speed Ethernet Controllers,” describes the two enhanced
three-speed Ethernet controllers on the device. These controllers provide 10/100/1Gb Ethernet
support with a set of media-independent interface options including MII and RGMII. The
controllers provide two full-duplex FIFO interface modes and quality of service support.
• Chapter 17, “I2C Interface,” describes the inter-IC (IIC or I
2
C) bus controllers of the device. These
synchronous, serial, bidirectional, multiple-master buses allow two-wire connection of devices,
such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCDs. The
device powers up in boot sequencer mode, which allows the I
2
C controllers to initialize
configuration registers.