Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-37
13.3.2.22 Endpoint Control Register 0 (ENDPTCTRL0)—Non-EHCI
Endpoint control register 0, shown in Figure 13-25, is not defined in the EHCI specification. Every device
will implement endpoint 0 as a control endpoint.
Table 13-31 describes the endpoint control register 0 fields.
15–3 — Reserved, should be cleared
2–0 ERCE Endpoint receive complete event. Each bit indicates a received event (OUT/SETUP) occurred and software
should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is
set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT. Writing a one will clear the
corresponding bit in this register. ERCE[2] corresponds to endpoint 2.
Offset 0x1C0 Access: Mixed
31 24 23 22 20 19 18 17 16 15 8 7 6 4 3 2 1 0
R
—
TXE
—
TXT
—TXS —
RXE
—
RXT
—RXS
W
Reset00000000 1 000 0 0 0 0 00000000 1 0000 00 0
Figure 13-28. Endpoint Control 0 (ENDPTCTRL0)
Table 13-31. ENDPTCTRL0 Register Field Descriptions
Bits Name Description
31–24 — Reserved, should be cleared.
23 TXE TX endpoint enable. Endpoint zero is always enabled.
0 Disable
1 Enable
22–20 — Reserved, should be cleared.
19–18 TXT TX endpoint type. Endpoint zero is always a control endpoint (00).
17 — Reserved, should be cleared.
16 TXS TX endpoint stall. Software can write a one to this bit to force the endpoint to return a STALL handshake to the
Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon
receipt of a new SETUP request.
1 Endpoint stalled
0 Endpoint OK
15–8 — Reserved, should be cleared.
7 RXE RX endpoint enable. Endpoint zero is always enabled.
0 Disabled
1 Enabled
6–4 — Reserved, should be cleared.
3–2 RXT RX endpoint type. Endpoint zero is always a control endpoint (00).
Table 13-30. ENDPTCOMPLETE Register Field Descriptions (continued)
Bits Name Description