Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-71
System software observes the resume event on the port, delays a port resume time (nominally 20
milliseconds), then terminates the resume sequence by clearing PORTSC[FPR] in the port. The host
controller receives the write of zero to PORTSC[FPR], terminates the resume sequence and clears
PORTSC[FPR] and PORTSC[SUSP]. Software can determine that the port is enabled (not suspended) by
sampling the PORTSC register and observing that the SUSP and FPR bits are zero. Software must ensure
that the host controller is running (that is, USBSTS[HCH] is a zero), before terminating a resume by
clearing the port's PORTSC[FPR] bit. If HCH is a one when PORTSC[FPR] is cleared, then SOFs will not
occur down the enabled port and the device will return to suspend mode in a maximum of 10 milliseconds.
Table 13-64 summarizes the wake-up events. Whenever a resume event is detected, USBSTS[PCI] is set.
If USBINTR[PCE] (port change interrupt enable) is a one, the host controller also generates an interrupt
on the resume event. Software acknowledges the resume event interrupt by clearing the USBSTS[PCI].
Table 13-64. Behavior During Wake-Up Events
Port Status and Signaling Type Signaled Port Response
Device State
D0 not D0
Port disabled, resume K-State received No effect N/A N/A
Port suspended, Resume K-State
received
Resume reflected downstream on signaled port.
PORTSC[FPR] is set. USBSTS[PCI] is set.
[1], [2] [2]
Port is enabled, disabled or suspended,
and the port's WKDSCNNT_E bit,
PORTSC[WKDS], is set. A disconnect is
detected.
Depending on the initial port state, the PORTSC Connect
(CCS) and Enable (PE) status bits are cleared, and the
Connect Change status bit (CSC) is set. USBSTS[PCI] is set.
[1], [2] [2]
Port is enabled, disabled or suspended,
and the port's WKDSCNNT_E bit,
PORTSC[WKDS], is cleared. A
disconnect is detected.
Depending on the initial port state, the PORTSC Connect
(CCS) and Enable (PE) status bits are cleared, and the
Connect Change status bit (CSC) is set. USBSTS[PCI] is set.
[1], [3] [3]
Port is not connected and the port's
WKCNNT_E bit is a one. A connect is
detected.
PORTSC Connect Status (CCS) and Connect Status Change
(CSC) bits are set. USBSTS[PCI] is set.
[1], [2] [2]
Port is not connected and the port's
WKCNNT_E bit is a zero. A connect is
detected.
PORTSC Connect Status (CCS) and Connect Status Change
(CSC) bits are set. USBSTS[PCI] is set.
[1], [3] [3]
Port is connected and the port's
WKOC_E bit is a one. An over-current
condition occurs.
PORTSC Over-current Active (OCA), Over-current Change
(OCC) bits are set. If Port Enable/Disable bit (PE) is a one, it is
cleared. USBSTS[PCI] is set
[1], [2] [2]
Port is connected and the port's
WKOC_E bit is a zero. An over-current
condition occurs.
PORTSC Over-current Active (OCA), Over-current Change
(OCC) bits are set. If Port Enable/Disable bit (PE) is a one, it is
cleared. USBSTS[PCI] is set.
[1], [3] [3]
1
Hardware interrupt issued if USBINTR[PCE] (port change interrupt enable) is set.
2
PME# asserted if enabled (Note: PME Status must always be set).
3
PME# not asserted.