Information

Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 1-3
– Per-packet configurable acceleration
– Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS
stacks, and ESP/AH IP-security headers
– Transmission from up to eight physical queues
– Reception to up to eight physical queues
— Full- and half-duplex Ethernet support (1000 Mbps supports only full-duplex):
– IEEE Std. 802.3 full-duplex flow control (automatic PAUSE frame generation or
software-programmed PAUSE frame generation and recognition)
— Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and IEEE
Std 802.1® virtual local area network (VLAN) tags and priority
— VLAN insertion and deletion
– Per-frame VLAN control word or default VLAN for each eTSEC
– Extracted VLAN control word passed to software separately
— Retransmission following a collision
— CRC generation and verification of inbound/outbound packets
— Programmable Ethernet preamble insertion and extraction of up to 7 bytes
— MAC address recognition:
– Exact match on primary and virtual 48-bit unicast addresses
– VRRP and HSRP support for seamless router fail-over
– Up to 16 exact-match MAC addresses supported
– Broadcast address (accept/reject)
– Hash table match on up to 512 multicast addresses
– Promiscuous mode
– 10K packet buffers to enable check-summing for jumbo packets
— Buffer descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet
programming models
— RMON statistics support
— MII management interface for control and status
• SerDes block with one lane
— Support for one 1 PCI Express controller
— Link-layer interfaces to PCI Express controller
— SerDes power-down/reset state machine for cold (power-on) or warm (software-initiated) reset
of SerDes, PHY, and controllers
• PCI Express
— Supports one interface supporting 1 width
— Compatible with the PCI Express 1.0a Specification
— Selectable operation as root complex or endpoint
— 32- and 64-bit addressing