Information

Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 1-5
— Master or slave I
2
C mode support
— On-chip digital filtering rejects spikes on the bus
• General purpose DMA engine
— Support for the DMA engine with the following features:
– Four DMA channels
– All data movement via dual-address transfers: read from source, write to destination
– Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations
– Channel activation using one of two methods (for both the methods, one activation per
execution of the minor loop is required):
– Explicit software initiation
– Initiation via a channel-to-channel linking mechanism for continuous transfers (independent
channel linking at end of minor loop and/or major loop)
– Support for fixed-priority and round-robin channel arbitration
– Channel completion reported via optional interrupt requests
— Support for scatter/gather DMA processing
• DUART
— Two 2-wire interfaces (RxD and TxD)
— Programming model compatible with the original 16450 UART and the PC16550D
• Serial peripheral interface (SPI)
— Master or slave support
• System timers
— Periodic interrupt timer
— Software watchdog timer
— Four general-purpose timers
• Enhanced secure digital host controller (eSDHC)
— Conforms to the SD Host Controller Standard Specification Version 2.0 including test event
register support
— Compatible with the MMC System Specification Version 4.0
— Compatible with the SD Memory Card Specification Version 2.0 and supports the high-capacity
SD memory card
— Compatible with the SD Card Specification, Part E1, SD Input/Output (SDIO) Card
Specification, Version 2.0
— Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC,
MMCplus, and RS-MMC cards
— Card bus clock frequency up to 50 MHz
— Supports 1-/4-bit SD and SDIO modes,
– Up to 200 Mbps of data transfer for SD/SDIO/MMC cards using four parallel data lines
— Supports single- and multi-block read and write