Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-10 Freescale Semiconductor
0x504 PCI Express BAR Prefetch Configuration Register
(PEX_BAR_PF)
R/W 0x0000_0400 14.4.7.3/14-74
PCI Express Extended Status and Control Register
0x590 PCI Express PME_To_Ack Timeout Register
(PEX_PME_TO_ACK_TOR)
Mixed 0x0019_5460 14.4.8.1/14-74
0x594 PCI Express PME_To_Ack Status Register
(PEX_PME_TO_ACK_SR)
w1c 0x0000_0000 14.4.8.2/14-75
0x5A0 PCI Express PCI Interrupt Mask Register
(PEX_SS_INTR_MASK)
Mixed 0x0000_003F 14.4.8.3/14-76
PCI Express CSB Bridge Registers
Global Registers
0x800–0
x804
Reserved — — —
0x808 PCI Express CSB Bridge Control register (PEX_CSB_CTRL) R/W 0x0000_0130 14.5.2.1/14-78
0x80C Reserved — — —
0x814 PCI Express DMA Descriptor Timer Register
(PEX_DMA_DSTMR)
R/W 0x0000_0000 14.5.2.2/14-79
0x818 Reserved — — —
0x81C PCI Express CSB Bridge Status register (PEX_CSB_STAT) R 0x0000_0000 14.5.2.3/14-79
0x820 Reserved — — —
PCI Express Outbound PIO Registers
0x840 PCI Express Outbound PIO Control Register
(PEX_CSB_OBCTRL)
R/W 0x0000_0000 14.5.3.1/14-80
0x844 PCI Express Outbound PIO Status Register
(PEX_CSB_OBSTAT)
w1c 0x0000_0000 14.5.3.2/14-81
0x848 Reserved — — —
PCI Express Inbound PIO Registers
0x8E0 PCI Express Inbound PIO Control Register
(PEX_CSB_IBCTRL)
R/W 0x0000_0000 14.5.4.1/14-82
0x8E4 PCI Express Inbound PIO Status Register (PEX_CSB_IBSTAT) w1c 0x0000_0000 14.5.4.2/14-83
0x8E8 Reserved — — —
PCI Express DMA Registers
0x990 Reserved — — —
0x9A0 PCI Express Write DMA Control Register (PEX_WDMA_CTRL) R/W 0x0000_0000 14.5.5.1/14-84
0x9A4 PCI Express Write DMA first Address Register
(PEX_WDMA_ADDR)
R/W 0x0000_0000 14.5.5.2/14-84
0x9A8 PCI Express Write DMA Status Register (PEX_WDMA_STAT) w1c 0x0000_0000 14.5.5.3/14-85
Table 14-3. PCI Express Memory Map (continued)
Offset Register Access Reset Section/Page
PCI Express—Block Base Address 0x0_9000