Information

Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 1-11
To provide for quality of service, transmission from up to eight queues is supported with priority-based
queue selection. Arbitration is a modified weighted round-robin queue selection with fair bandwidth
allocation.
On receive, packets may be distributed to any of the 64 virtual receive queues overlaid onto the 8 physical
receive queues. A table-oriented queue filing strategy is provided based on 16 header fields or flags. Frame
rejection is supported for filtering applications.
Filing can be based on Ethernet, IP, and TCP/UDP properties, including VLAN fields, Ether-type, IP
protocol type, IP TOS or differentiated services, IP source and destination addresses, TCP/UDP port
numbers, or user-defined bit fields.
1.2.4 SerDes PHY
The SerDes PHY block includes the SerDes PHY, the protocol converter per protocol, the protocol mux,
and the control registers and control logic.
The SerDes PHY block has the following features:
• Support for one 1 PCI Express interface
• Link-layer interfaces to PCI Express
• Memory-mapped registers with 256-byte address region
• SerDes power-down/reset state machine for cold (power-on) or warm (software-initiated) reset of
SerDes, PHY, and controllers
The SerDes PHY block supports the following mode of operation:
• One lane running 1 PCI Express at 2.5 Gbps
1.2.5 PCI Express Interface
The MPC8308 supports a PCI Express interface compliant with the PCI Express Base Specification
Revision 1.0a. It is able to act as either root complex or endpoint. It only supports virtual channel 0 (VC0)
and eight traffic classes (TC0–TC7). The maximum supported packet payload size is 128 bytes.
The physical layer supports single 1 lane width running at the specified data rate of 2.5 Gbauds.
Inbound INTx transaction is supported and change the state of a level-sensitive interrupt presented to the
PIC. Outbound INTx transaction is supported. Message signaled interrupt (MSI) transaction is supported
and controls up to 256 interrupt sources within the PIC. Outbound MSI transaction may be created by
software using the MSI Capability Register Sets.
The physical layer of the PCI Express interface operates at a 2.5-Gbaud data rate.
1.2.6 Universal Serial Bus (USB) 2.0
The USB 2.0 controller offers operation as a host or device. The USB controller provides point-to-point
connectivity, which complies with the Universal Serial Bus Revision 2.0 Specification. The USB
controllers can be configured to operate as a stand-alone host or stand-alone device. See Figure 1-3 for
more information.