Information

PCI Express Interface Controller

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

Freescale Semiconductor 14-15

NOTE

The registers described in this section use little-endian byte ordering.

Software running on the local processor in big-endian mode must byte-swap

the data. No byte swapping occurs when the registers are accessed from the

PCI Express bus.

14.4.1.1 PCI Express Vendor ID Register

The vendor ID register, shown in Figure 14-3, identifies the manufacturer of the device.

Table 14-4 describes the vendor ID register fields.

14.4.1.2 PCI Express Device ID Register

The device ID register, shown in Figure 14-4, identifies the device.

Table 14-5 describes the device ID register fields.

14.4.1.3 PCI Express Command Register

The PCI Express command register, shown in Figure 14-5, controls the ability to generate and respond to

PCI Express cycles. The error control and status bits in the command and status registers control

PCI Express-compatible error reporting. Note that PCI Express advanced error reporting is controlled by

Offset 0x000 Access: Read-only

15 0

R Vendor ID

Reset0001100101010111

Figure 14-3. PCI Express Vendor ID Register

Table 14-4. PCI Express Vendor ID Register Field Description

Bits Name Description

15–0 Vendor ID 0x1957 (Freescale)

Offset 0x002 Access: Read-only

15 0

RDevice ID

Reset Device-specific; see field description

Figure 14-4. PCI Express Device ID Register

Table 14-5. PCI Express Device ID Register Field Description

Bits Name Description

15–0 Device ID Device ID. This field identifies the device.

C006 MPC8308