Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-19
. Table 14-9 describes the class code register fields.
14.4.1.7 PCI Express Cache Line Size Register
The cache line size register, shown in Figure 14-9, is provided for legacy compatibility (PCI 2.3); it is not
used for PCI Express device functionality.
Table 14-10 describes the cache line size register.
14.4.1.8 PCI Express Latency Timer Register
The latency timer register, shown in Figure 14-10, is provided for legacy compatibility (PCI 2.3); it is not
used for PCI Express device functionality.
Table 14-9. PCI Express Class Code Register Fields Description
Bits Name Description
23–16 Base Class 0x0B—Processor
15–8 Subclass 0x20—PowerPC
7–0 Programming
Interface
0x00—RC mode
0x00—EP mode
Offset 0x00C Access: Read/Write
7 0
R
Cache Line Size
W
Reset All zeros
Figure 14-9. PCI Express Bus Cache Line Size Register
Table 14-10. PCI Express Bus Cache Line Size Register Fields Description
Bits Name Description
7–0 Cache Line
Size
Represents the cache line size of the processor in terms of 32-bit words (eight 32-bit words = 32 bytes).
Note that for PCI Express operation this register is ignored.
Offset 0x00D Access: Read-only
7 0
R Latency Timer
W
Reset All zeros
Figure 14-10. PCI Express Latency Timer Register