Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-23
14.4.2.1.2 Base Address Registers 2 and 4 (BAR2/BAR4)
BAR2 and BAR4, shown in Figure 14-14, define the lower portion of the 64-bit inbound memory
windows.
Table 14-14 describes the PCI Express 64-bit low memory BAR2 and BAR4 fields.
14.4.2.1.3 Base Address Registers 3 and 5 (BAR3/BAR5)
BAR3/BAR5, shown in Figure 14-15, define the upper portion of the 64-bit inbound memory windows.
Table 14-15 describes the BAR3 and BAR5 fields.
Offset 0x018 (EP mode only)
0x020 (EP mode only)
Access: Mixed
31 12 11 4 3 2 1 0
R
ADDRESS —
PREF TYPE MemSp
W
Reset0000000000000000000000000000 1 1 0 0
Figure 14-14. 64-Bit Low Memory Base Address Register (BAR2)
Table 14-14. BAR2 and BAR4 Register Fields Description
Bits Name Description
31–12 ADDRESS Indicates the lower portion of the base address where the inbound memory window begins. The number
of upper bits that the device allows to be writable is selected through the PCI Express BAR configuration
registers (EP mode).
11–4 — Reserved. The device allows a 4 Kbyte window minimum.
3 PREF Prefetchable. This bit is determined by PCI Express BAR prefetch configuration register
(PEX_BAR_PF).
2–1 TYPE Type.
0b10 Locate anywhere in 64-bit address space.
0 MemSp Memory space indicator
Offset 0x01C (EP mode only)
0x024 (EP mode only)
Access: Read/Write
31 0
R
ADDRESS
W
Reset All zeros
Figure 14-15. 64-Bit High Memory Base Address Registers 3 and 5 (BAR3/BAR5)
Table 14-15. BAR3 and BAR5 Register Fields Description
Bits Name Description
31–0 ADDRESS Indicates the upper portion of the base address where the inbound memory window begins. Since the
local (CSB) address space of the device is only 32 bits (4 Gbytes), this register is all masked (all ones)
when accessed during the enumeration sequence.