Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-39
14.4.4.5 PCI Express Power Management Data Register
The PCI Express power management data register is shown in Figure 14-45.
Table 14-43 describes the PCI Express power management data register fields.
14.4.4.6 PCI Express Capability ID Register
The PCI Express capability ID register is shown in Figure 14-46.
8 PME_EN PME Enable
7–2 — Reserved
1–0 Power State Power state. Indicates the current power state of the function.
00 D0
01 D1
02 D2
03 D3
Offset 0x04B Access: Read-only
7 0
RData
W
Reset All zeros
Figure 14-45. PCI Express Power Management Data Register
Table 14-43. PCI Express Power Management Data Register Fields Description
Bits Name Description
7–0 Data —
Offset 0x04C Access: Read-only
7 0
R PCI Express Capability ID
W
Reset00010000
Figure 14-46. PCI Express Capability ID Register
Table 14-42. PCI Express Power Management Status and Control Register Fields Description (continued)
Bits Name Description