Information

Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
1-14 Freescale Semiconductor
— Block write locking to ensure system security and integrity
• Three user-programmable machines (UPMs)
— Programmable-array-based machine controls external signal timing with a granularity of up to
one quarter of an external bus clock period
— User-specified control-signal patterns run when an internal master requests a single-beat or
burst read or write access
— UPM refresh timer runs a user-specified control signal pattern to support refresh
— User-specified control-signal patterns can be initiated by software
— Each UPM can be defined to support devices with depths of 64, 128, 256, and 512 Kbytes, and
1, 2, 4, 8, 16, 32, 64 Mbytes
— Support for 8- and 16-bit devices
— Page mode support for successive transfers within a burst
• Optional monitoring of transfers between local bus internal masters and local bus slaves (local bus
error reporting)
1.2.8 Integrated Programmable Interrupt Controller (IPIC)
The Integrated Programmable Interrupt Controller (IPIC) implements the necessary functions to provide
a flexible solution for general-purpose interrupt control. The IPIC includes the following features:
• Functional and programming models are compatible with the MPC8260 interrupt controller
• Support for external and internal discrete interrupt sources
• Support for one external (optional) and seven internal machine checkstop interrupt sources
• Programmable highest priority request
• Two programmable priority mixed groups of four on-chip and four external interrupt signals with
two priority schemes for each group: grouped and spread
• Four programmable priority internal groups of eight on-chip interrupt signals with two priority
schemes for each group: grouped and spread
• Priority interrupts can be programmed to support a critical (cint) or system management (smi)
interrupt type
• External and internal interrupts directed to a host processor
• Unique vector number for each interrupt source
• IPIC can support external interrupt request with programmable triggering mechanism. It can be
programmed to use one of the following mechanisms:
— Active low level triggering
— Active high level triggering
— Raising edge triggering
— Falling edge triggering