Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-48 Freescale Semiconductor
14.4.4.18 PCI Express Root Control Register (RC Mode Only)
The PCI Express root control register is shown in Figure 14-58.
Table 14-56 describes the PCI Express root control register fields.
14.4.4.19 PCI Express Root Status Register (RC Mode Only)
The PCI Express root status register is shown in Figure 14-59.
Table 14-57 describes the PCI Express root status register fields.
Offset 0x068 Access: Read/Write
15 43 2 1 0
R
— PMEIE SEFEE SENFEE SECEE
W
Reset All zeros
Figure 14-58. PCI Express Root Control Register
Table 14-56. PCI Express Root Control Register Fields Description
Bits Name Description
15–4 — Reserved
3 PMEIE PME interrupt enable.
2 SEFEE System error on fatal error enable.
1 SENFEE System error on non-fatal error enable.
0 SECEE System error on correctable error enable.
Offset 0x06C Access: Mixed
31 18 17 16
R — PMEP PMES
W
w1c
Reset All zeros
15 0
R PME Requestor ID
W
Reset All zeros
Figure 14-59. PCI Express Root Status Register
Table 14-57. PCI Express Root Status Register Fields Description
Bits Name Description
31–18 — Reserved
17 PMEP PME pending.