Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-53
14.4.5.1 PCI Express Advanced Error Reporting Capability ID Register
The PCI Express advanced error reporting capability ID register is shown in Figure 14-66.
Table 14-63 describes the PCI Express advanced error reporting capability ID register fields.
14.4.5.2 PCI Express Uncorrectable Error Status Register
The PCI Express uncorrectable error status register is shown in Figure 14-67. When a particular bit of this
status register is set, it indicates that the error has occurred.
Offset 0x100 Access: Read-only
31 20 19 16
R Next Capability Pointer Capability Version
W
Reset0001001110000001
15 0
R Capability ID
W
Reset0000000000000001
Figure 14-66. PCI Express Advanced Error Reporting Capability ID Register
Table 14-63. PCI Express Advanced Error Reporting Capability ID Register Fields Description
Bits Name Description
13–20 Next Capability Pointer Note: even though the default value of this field is not NULL, it should be considered so
by the software.
19–16 Capability Version —
15–0 Capability ID Advanced error reporting capability.
Offset 0x104 Access: w1c
31 21 20 19 18 17 16
R
—
URE ECRCE MTLP RXO UC
W w1c w1c w1c w1c w1c
Reset All zeros
15 14 13 12 11 5 4 3 1 0
R CA CTO FCPE PTLP
—
DLPE
—
TE
W w1c w1c w1c w1c w1c w1c
Reset All zeros
Figure 14-67. PCI Express Uncorrectable Error Status Register