Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-88 Freescale Semiconductor
14.5.6 Mailbox Registers
This section describes the following registers:
• Section 14.5.6.1, “PCI Express Outbound Mailbox Control Register (PEX_OMBCR)”
• Section 14.5.6.2, “PCI Express Outbound Mailbox Data Register (PEX_OMBDR)”
• Section 14.5.6.3, “PCI Express Inbound Mailbox Control Register (PEX_IMBCR)”
• Section 14.5.6.4, “PCI Express Inbound Mailbox Data Register (PEX_IMBDR)”
14.5.6.1 PCI Express Outbound Mailbox Control Register (PEX_OMBCR)
PEX_OMBCR, shown in Figure 14-108, controls the generation of an outbound interrupt from the CSB
local host to the PCI Express and indicates that the local host has programmed the data mailbox register,
and it is ready to be read. Setting the ready bit generates an interrupt to the PCI Express host if enabled.
The PCI Express host should clear the ready bit after reading the data mailbox register.
Table 14-106 defines the bit fields of PEX_OMBCR.
14.5.6.2 PCI Express Outbound Mailbox Data Register (PEX_OMBDR)
PEX_OMBDR, shown in Figure 14-109, contains the data to be read by the PCI Express host when it
receives an interrupt.
Table 14-107 defines the bit fields of PEX_OMBDR.
Offset 0xB20 Access: Read/Write
31 10
R
— READY
W
Reset All zeros
Figure 14-108. PCI Express Outbound Mailbox Control Register (PEX_OMBCR)
Table 14-106. PEX_OMBCR Register Fields Description
Bits Name Description
31–1 — Reserved
0 READY Outbound mailbox ready. If set, indicates that mailbox has valid data to be read by the PCI Express host
and generates an interrupt if enabled.
Offset 0xB24 Access: Read/Write
31 0
R
MBD
W
Reset All zeros
Figure 14-109. MPCI Express Outbound Mailbox Data Register (PEX_OMBDR)