Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-117
As RC the PCI Express controller configuration access mechanism utilizes a memory-mapped address
space to access device configuration registers. To achieve this, software can program the TYPE field of
the PEX_OWARn register to 0x0 in one of the outbound ATMU windows to perform a configuration
access. The other bit fields of the PEX_OWARn register should be programmed as below:
• TC = 0x0
• NSNP = 0
•RLXO = 0
•EN = 1
The SIZE field of the PEX_OWARn register should be set to a value to correspond with the BA (base
address) field of the base address register (PEX_OWBARn), normally based on the Bus Number(s) of the
downstream PCI Express device(s) to be accessed. The base address registers, PEX_OWBARn, set the
CSB address window for the configuration transactions. The translation address registers,
PEX_OWTARLn, can be used to define the translated PCI Express address of the CSB-based
configuration transaction.
Once the PCI Express outbound window attributes register (PEX_OWARn), base address register
(PEX_OWARn) and translation address register (PEX_OWTARLn) are fully defined, a CSB-based
memory transaction hitting the defined base address register will be converted to an external PCI Express
configuration transaction cycle appeared on the downstream link of the PCI Express RC controller. In this
case, the CSB memory address determines the configuration register accessed and the memory data returns
the contents of the addressed register. Software must only issue 4-byte or less access to the ATMU
configuration window and the access cannot cross a 4-byte boundary.
The mapping from the CSB local address to PCI Express configuration space is defined by the Outbound
ATMU as in a memory transaction. The actual PCI Express configuration header will be formatted from
the CSB address and the ATMU translation, defined by PEX_OWTARLn.
The formatted address defines the configuration transactions parameter, as shown in Table 14-138. Note
that there is no byte swapping for the address itself, although the programming of the registers content do
require byte swapping. The table also translates between the bit ordering commonly used by the PowerPC
terminology (0–31) and the bit ordering used by the PCI Express terminology (31–0).
Table 14-138. Configuration Address Mapping
CSB Address Bits
Numbering
PCI Express Address Bits
Numbering
PCI Express Configuration Space
0
–731–24 Bus number
8–12 23–19 Device number
13–15 18–16 Function number
16–19 15–12 Reserved
20–23 11–8 Extended register number
24
–29 7–2 Register number