Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-133
The number of ways, n, is software configurable. In this mode, n descriptors are written in contiguous
memory locations. The implicit address of the next descriptor is the next memory location. The last
descriptor in the contiguous block contains the explicit address pointer of the next set of n descriptors.
Address 0x0 will never be part of the chain since it should close the chain. Non-contiguous valid
descriptors are not supported. If the valid bit of a descriptor in the chain is not set, all of the succeeding
descriptors should also have the valid bit as zero.
The software need to follow the following sequence on receiving a chain transfer done interrupt:
1. Software receives an interrupt for chain transfer done.
2. Software polls the main memory and waits for descriptor done bit to be set (bit 32 in the descriptor).
This guarantees that the final data has been written into memory for read DMA. For write DMA,
it guarantees that the final data has been sent to PCI Express controller. If a read is sent to the same
location, PCI Express controller guarantees that the outbound read will not bypass the outbound
write.
The host can reuse the descriptor memory after the DMA/bridge logic processes it. The exact handshake
between the hardware and software is described later in this chapter. The DMA registers are described in
Section 14.5.5, “DMA Registers.”
When n > 1, the hardware uses this knowledge to prefetch descriptors in advance, thereby reducing
possible holes in transmission. This might be useful for applications that request several small DMA
transfer requests, such as an Ethernet traffic. For applications that request large data transfers, the effect
on performance due to descriptor fetching is not significant.
14.8.4.2 Block Descriptors
Block descriptors are a special case of chain descriptor in which all the descriptors are part of a single array.
A portion of host memory is reserved to store the descriptors. The starting address of this block is indicated
in the DMA control register. This block of memory serves as a circular buffer. Software writes the first
descriptor to the first address in the descriptor block address space. Subsequent descriptors are written in
the consecutive locations until the last location in the descriptor space. After that, the next descriptor is
again written into the first location. All descriptors except the one written into the last descriptor location
in the block have an implicit address that points to the immediate next descriptor location in the block. The
last descriptor contains an explicit address pointer to the first descriptor location of the block. Software
must ensure that a descriptor is processed by hardware before overwriting it. Figure 14-144 illustrates the
organization of the block descriptors in memory.
Figure 14-144. Block Descriptor Organization in Host Memory
The DMA can fetch prefetch a configurable number of descriptors in a single shot. This number depends
on the chain organization (n) as well as the number of descriptor registers in the DMA engine.
D1
D2
•
•
Dn
Descriptor Memory
Space