Information

SerDes PHY
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 15-5
17–19 TXEQA Sets the peak value for output swing of transmitters and the amount of transmit equalization for lane A.
Transmit equalization selection bus for lane A.
000 No equalization
001 1.09 relative amplitude
010 1.2 relative amplitude
011 1.33 relative amplitude
100 1.5 relative amplitude
101 1.71 relative amplitude
110 2.0 relative amplitude
111 Reserved
Recommended setting per protocol is PCI Express: 100
20–23 — Reserved
1
24 SDPD SerDes power down. This power down signal shuts down the PLL, all of the receiver amplifiers, all of the
samplers and places the transmitters in 3-state.
0 Application mode
1 Block power down
25 — Reserved
1
26 IACCA Used to set on-chip AC coupling in the receiver in lane A.
0 Disable on-chip AC coupling
1 Enable on-chip AC coupling
Recommended setting per protocol is PCI Express: 1
27–29 — Reserved
1
30 RXEIA When asserted, places lane A into receiver electrical idle state.
0 Lane A is not ‘forced’ into receive electrical idle state
1 Place lane A into electrical idle state
Recommended setting per protocol is PCI Express: 0
31 — Reserved
1
1
Bits with reset value of one must be written as one during any write operation.
NOTE
While writing to this register, bit 7, 20, 21, and 27 should be set to 1.
Table 15-3. SRDSCR0 Field Descriptions (continued)
Bits Name Description