Information

SerDes PHY
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
15-8 Freescale Semiconductor
15.3.4 SerDes Control Register 3 (SRDSCR3)
SRDSCR3, shown in Figure 15-5, contains the functional control bits for the SerDes logic.
Table 15-6 describes the SRDSCR3.
22–23 PEICA PCII-EXP Receiver electrical idle detection control
00 Exit from idle ~85 UI and unexpected idle detect ~1 s (application mode)
01 Exit from idle ~85 UI and unexpected idle detect ~10 s
10 Exit from idle ~45 UI and unexpected idle detect ~1 s
11 Bypass
24–31 — Reserved
Offset 0x0C Access: Read only
0 5678 15
R
—SDFMA —
W
Reset0000000100000001
16 31
R
—
W
Reset All zeros
Figure 15-5. SerDes Control Register 3 (SRDSCR3)
Table 15-6. SRDSCR3 Field Descriptions
Bits Name Description
0–5 — Reserved
1
1
Bits with reset value of one must be written as one during any write operation.
NOTE
While writing to this register, bit 15 should be set to 1.
6–7 SDFMA Sets the bandwidth of the digital filter to optimize for given frequency offset specification for lane A.
00 Reserved
01 600 ppm (PCI Express)
10 Reserved
11 Reserved
Recommended setting per protocol is PCI Express: 01
8–31 — Reserved
1
Table 15-5. SRDSCR2 Field Descriptions (continued)
Bits Name Description