Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-5
controlled by software using the serial management interface (MDC/MDIO signals) to the
transceiver.
Clause 22.2.4 of the IEEE 802.3 specification describes the MII management interface.
• MAC address recognition options
The options supported are promiscuous, broadcast, exact unicast address match, exact unicast
virtual address match to support router redundancy, and multicast hash match. For detailed
descriptions refer to Section 16.6.2.7, “Frame Recognition.”
• Receive frame parsing options
Frame parsing options are to disable parsing (no TCP/IP off-load), IP header parsing, and TCP or
UDP parsing. Parsing must be enabled to make use of receive queue filing algorithms. The options
are detailed in Section 16.6.3, “TCP/IP Off-Load.”
• Receive queue selection options
Received frames are by default sent to a single buffer descriptor ring. If multiple receive queues
are enabled, a receive queue filer can be programmed with selection criteria to differentiate
received frames and file them to different buffer descriptor rings. See Section 16.6.4, “Quality of
Service (QoS) Provision,” for detailed descriptions.
• TCP/IP transmit options
Frames for transmission may be sent as-is, with IP header processing, or TCP header processing.
The transmit buffer descriptors, described in Section 16.6.7.2, “Transmit Data Buffer Descriptors
(TxBD),” enable these options and operate with parameters prepended to frame buffers, as
described in Section 16.6.3, “TCP/IP Off-Load.”
• Transmit queue selection options
The options supported are single transmit queue, priority-based queue selection, and modified
weighted round-robin queueing. These options are described further in Section 16.5.3.2.1,
“Transmit Control Register (TCTRL).”
• RMON support
Standard Ethernet interface management information base (MIBs) can be generated through the
RMON MIB counters.
• Internal loop back supported for all interfaces except when configured for half-duplex operation
Internal loop back mode is selected through the loop back bit in the MACCFG1 register. See
Section 16.7.1, “Interface Mode Configuration,” for details.
16.4 External Signals Description
This section defines the eTSEC interface signals. The buses are described using the bus convention used
in IEEE 802.3 because the PHY follows this same convention. (That is, TxD[3–0] means 0 is the lsb.) Note
that except for external physical interfaces the buses and registers follow a big-endian format, where 0
denotes the msb.