Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-92 Freescale Semiconductor
16.5.3.6.30 Transmit Deferral Packet Counter (TDFR)
Figure 16-80 describes the definition for the TDFR register.
Table 16-84 describes the fields of the TDFR register.
16.5.3.6.31 Transmit Excessive Deferral Packet Counter (TEDF)
Figure 16-81 describes the definition for the TEDF register.
Table 16-85 describes the fields of the TEDF register.
Offset eTSEC1:0x2_46F4; eTSEC2:0x2_56F4 Access: Read/Write
0 19 20 31
R
—TDFR
W
Reset All zeros
Figure 16-80. Transmit Deferral Packet Counter Register Definition
Table 16-84. TDFR Field Descriptions
Bits Name Description
0–19 — Reserved
20–31 TDFR Transmit deferral packet counter. Increments for each frame, which was deferred on its first transmission
attempt. This count does not include frames involved in collisions.
Offset eTSEC1:0x2_46F8; eTSEC2:0x2_56F8 Access: Read/Write
0 19 20 31
R
—TEDF
W
Reset All zeros
Figure 16-81. Transmit Excessive Deferral Packet Counter Register Definition
Table 16-85. TEDF Field Descriptions
Bits Name Description
0–19 — Reserved
20–31 TEDF Transmit excessive deferral packet counter. Increments for frames aborted which were deferred for an
excessive period of time (3036 byte times).