Information

Enhanced Three-Speed Ethernet Controllers

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

16-104 Freescale Semiconductor

16.5.3.6.48 Receive Filer Rejected Packet Counter (RREJ)

Figure 16-98 describes the definition for the RREJ register.

Table 16-102 describes the fields of the RREJ register.

16.5.3.7 Hash Function Registers

This section provides detailed descriptions of the registers used for hash functions. All of the registers are

32 bits wide. The DA field of every received frame is processed through a 32-bit CRC generator (CRC-32

polynomial), and the 8 or 9 most significant bits of the CRC are mapped to a hash table entry. The user

can enable a hash entry by setting its bit. A hash entry usually represents a set of addresses. A hash table

hit occurs if the DA CRC result points to an enabled hash entry. Software may need to further filter the

address in order to eliminate false-positive hits in the hash table.

If RCTRL[GHTX] = 0, the 8 most significant bits of the CRC are used as the hash table index. In this case,

registers IGADDR0–IGADDR7 comprise a 256-entry hash table exclusively for individual (unicast)

address matching, while registers GADDR0–GADDR7 comprise a 256-entry hash table for group

(multicast) address matching. If RCTRL[GHTX] = 1, the group hash table is extended to all 512 entries,

and the 9 most significant bits of the CRC are used as the hash table index. In this case, registers

IGADDR0–IGADDR7 hold hash table entries 0–255 for group addresses, while registers

GADDR0–GADDR7 hold entries 256–511 of the extended group hash table.

For more information on the hash algorithm, see Section 16.6.2.7.2, “Hash Table Algorithm.”

30 — Reserved

31 M2TDP Mask register 2 TDRP counter carry bit mask

Offset eTSEC1:0x2_4740; eTSEC2:0x2_5740 Access: Read/Write

0910 31

— RREJ

Reset All zeros

Figure 16-98. Receive Filer Rejected Packet Counter Register Definition

Table 16-102. RREJ Field Descriptions

Bits Name Description

0–9 — Reserved

10–31 RREJ Receive filer rejected packet counter. Increments for each frame with valid CRC received, but rejected by

the receive queue filer—either due to a matching rule that asserted the REJ flag or due to filing to a RxBD

ring that was not enabled (see IEVENT[FIQ] error).

Table 16-101. CAM2 Field Descriptions (continued)

Bits Name Description