Information
Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-105
16.5.3.7.1 Individual/Group Address Registers 0–7 (IGADDRn)
The IGADDRn registers are written by the user. Together these registers represent, depending on
RCTRL[GHTX], either the 256 entries of the individual address hash table, or the first 256 entries of the
extended group address hash table used in the address recognition process. The user can enable a hash
entry by setting the appropriate bit. A hash table hit occurs if the DA CRC-32 result points to an enabled
hash entry.
Figure 16-99 describes the definition for the IGADDRn register.
Table 16-103 describes the fields of the IGADDRn register.
16.5.3.7.2 Group Address Registers 0–7 (GADDRn)
The GADDRn registers are written by the user. Together these registers represent, depending on
RCTRL[GHTX], either the 256 entries of the group address hash table, or the last 256 entries of the
extended group address hash table used in the address recognition process. The user can enable a hash
entry by setting the appropriate bit. A hash table hit occurs if the DA CRC result points to an enabled hash
entry. Figure 16-100 describes the definition for the GADDRn register.
Offset eTSEC1:0x2_4800+4n; eTSEC2:0x2_5800+4n Access: Read/Write
0 31
R
IGADDRn
W
Reset All zeros
Figure 16-99. IGADDRn Register Definition
Table 16-103. IGADDRn Field Descriptions
Bits Name Description
0–31 IGADDRn Represents the 32-bit value associated with the corresponding register. When RCTRL[GHTX] = 0,
IGADDR0 contains entries 0–31 of the 256-entry individual hash table and IGADDR7 represents entries
224–255. When RCTRL[GHTX] = 1, IGADDR0 contains entries 0–31 of the 512-entry extended group hash
table and IGADDR7 represents entries 224–255.
Offset eTSEC1:0x2_4880+4n; eTSEC2:0x2_5880+4n Access: Read/Write
0 31
R
GADDRn
W
Reset All zeros
Figure 16-100. GADDRn Register Definition