Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-106 Freescale Semiconductor
Table 16-104 describes the fields of the GADDRn register.
16.5.3.8 DMA Attribute Registers
This section describes the two eTSEC DMA attribute registers.
16.5.3.8.1 Attribute Register (ATTR)
The attribute register defines memory access attributes and transaction types used to access buffer
descriptors, to write receive data, and to read transmit data. Snoop enable attributes may be set for reading
buffer descriptors and for reading transmit data.
Figure 16-101 describes the definition for the ATTR register.
Table 16-105 describes the fields of the ATTR register.
16.5.3.8.2 Attribute Extract Length and Extract Index Register (ATTRELI)
The ATTRELI registers are written by the user to specify the extract index and extract length for extracting
received frames. The extract length is typically set to the expected length of extracted packet headers.
Figure 16-102 describes the definition for the ATTRELI register.
Table 16-104. GADDRn Field Descriptions
Bits Name Description
0–31 GADDRn Represents the 32-bit value associated with the corresponding register. When RCTRL[GHTX] = 0,
GADDR0 contains entries 0–31 of the 256-entry group hash table and GADDR7 represents entries
224–255. When RCTRL[GHTX] = 1, GADDR0 contains entries 256–287 of the 512-entry extended group
hash table and GADDR7 represents entries 480–511.
Offset eTSEC1:0x2_4BF8; eTSEC2:0x2_5BF8 Access: Read/Write
0 23 24 25 26 31
R
— RDSEN RBDSEN —
W
Reset All zeros
Figure 16-101. ATTR Register Definition
Table 16-105. ATTR Field Descriptions
Bits Name Description
0–23 — Reserved
24 RDSEN Rx data snoop enable.
0 Disables snooping of all receive frames data to memory.
1 Enables snooping of all receive frames data to memory.
25 RBDSEN RxBD snoop enable.
0 Disables snooping of all receive BD memory accesses.
1 Enables snooping of all receive BD memory accesses.
26–31 — Reserved