Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
14 Freescale Semiconductor
Bus Signal Timing
12 Bus Signal Timing
The maximum bus speed that the MPC852T supports is 66 MHz. Table 7 shows the frequency ranges for
standard part frequencies.
Table 9 provides the bus operation timing for the MPC852T at 33, 40, 50, and 66 MHz.
The timing for the MPC852T bus shown assumes a 50-pF load for maximum delays and a 0-pF load for
minimum delays. CLKOUT assumes a 100-pF load maximum delay
Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)
Part Frequency
50 MHz 66 MHz
Min Max Min Max
Core 40 50 40 66.67
Bus 40 50 40 66.67
Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)
Part Frequency
50 MHz 66 MHz 80 MHz 100 MHz
Min Max Min Max Min Max Min Max
Core 40 50 40 66.67 40 80 40 100
Bus 2:1 20 25 20 33.33 20 40 20 50
Table 9. Bus Operation Timings
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
B1 Bus period (CLKOUT) See Ta ble 7 ————————ns
B1a EXTCLK to CLKOUT phase skew—If
CLKOUT is an integer multiple of
EXTCLK, then the rising edge of EXTCLK
is aligned with the rising edge of CLKOUT.
For a non-integer multiple of EXTCLK, this
synchronization is lost, and the rising
edges of EXTCLK and CLKOUT have a
continuously varying phase skew.
–2 +2 –2 +2 –2 +2 –2 +2 ns
B1b CLKOUT frequency jitter peak-to-peak — 1 — 1 — 1 — 1 ns
B1c Frequency jitter on EXTCLK
1
— 0.50 — 0.50 — 0.50 — 0.50 %
B1d CLKOUT phase jitter peak-to-peak for
OSCLK ≥ 15 MHz
—4—4—4—4 ns
CLKOUT phase jitter peak-to-peak for
OSCLK < 15 MHz
—5—5—5—5 ns
B2 CLKOUT pulse width low (MIN = 0.4 × B1,
MAX = 0.6 × B1)
12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns