Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
18 Freescale Semiconductor
Bus Signal Timing
B29b CS negated to D(0:31), DP(0:3), High Z
GPCM write access, ACS = 00,
TRLX = 0,1 and CSNT = 0
(MIN = 0.25 × B1 – 2.00)
5.60 — 4.30 — 3.00 — 1.80 — ns
B29c CS
negated to D(0:31), DP(0:3) High-Z
GPCM write access, TRLX = 0, CSNT = 1,
ACS = 10, or ACS = 11 EBDF = 0
(MIN = 0.50 × B1 – 2.00)
13.20 — 10.50 — 8.00 — 5.60 — ns
B29d WE
(0:3)/BS_B[0:3] negated to D(0:31),
DP(0:3) High-Z GPCM write access, TRLX
= 1, CSNT = 1, EBDF = 0
(MIN = 1.50 × B1 – 2.00)
43.50 — 35.50 — 28.00 — 20.70 — ns
B29e CS
negated to D(0:31), DP(0:3) High-Z
GPCM write access, TRLX = 1, CSNT = 1,
ACS = 10, or ACS = 11 EBDF = 0
(MIN = 1.50 × B1 – 2.00)
43.50 — 35.50 — 28.00 — 20.70 — ns
B29f WE
(0:3/BS_B[0:3]) negated to D(0:31),
DP(0:3) High Z GPCM write access,
TRLX = 0, CSNT = 1, EBDF = 1
(MIN = 0.375 × B1 – 6.30)
8
5.00 — 3.00 — 1.10 — 0.00 — ns
B29g CS
negated to D(0:31), DP(0:3) High-Z
GPCM write access, TRLX = 0, CSNT = 1
ACS = 10 or ACS = 11, EBDF = 1
(MIN = 0.375 × B1 – 6.30)
8
5.00 — 3.00 — 1.10 — 0.00 — ns
B29h WE
(0:3)/BS_B[0:3] negated to D(0:31),
DP(0:3) High Z GPCM write access,
TRLX = 1, CSNT = 1, EBDF = 1
(MIN = 0.375 × B1 – 3.30)
38.40 — 31.10 — 24.20 — 17.50 — ns
B29i CS
negated to D(0:31), DP(0:3) High-Z
GPCM write access, TRLX = 1, CSNT = 1,
ACS = 10 or ACS = 11, EBDF = 1
(MIN = 0.375 × B1 – 3.30)
38.40 — 31.10 — 24.20 — 17.50 — ns
B30 CS
, WE(0:3)/BS_B[0:3] negated to
A(0:31), BADDR(28:30) Invalid GPCM
write access
9
(MIN = 0.25 × B1 – 2.00)
5.60 — 4.30 — 3.00 — 1.80 — ns
B30a WE
(0:3)/BS_B[0:3] negated to A(0:31),
BADDR(28:30) Invalid GPCM, write
access, TRLX = 0, CSNT = 1, CS
negated
to A(0:31) invalid GPCM write access
TRLX = 0, CSNT =1 ACS = 10, or
ACS == 11, EBDF = 0
(MIN = 0.50 × B1 – 2.00)
13.20 — 10.50 — 8.00 — 5.60 — ns
Table 9. Bus Operation Timings (continued)
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max