Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
Freescale Semiconductor 33
Bus Signal Timing
Figure 21 provides the timing for the synchronous external master access that the GPCM controls.
Figure 21. Synchronous External Master Access Timing (GPCM Handled ACS = 00)
Figure 22 provides the timing for the asynchronous external master memory access that the GPCM
controls.
Figure 22. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)
Figure 23 provides the timing for the asynchronous external master control signals negation.
Figure 23. Asynchronous External Master—Control Signals Negation Timing
CLKOUT
TS
A[0:31],
TSIZ[0:1],
R/W
, BURST
CSx
B41 B42
B40
B22
CLKOUT
AS
A[0:31],
TSIZ[0:1],
R/W
CSx
B39
B40
B22
AS
CSx, WE[0:3],
OE
, GPLx,
BS
[0:3]
B43