Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
4 Freescale Semiconductor
Features
• Two baud rate generators
— Independent (can be connected toany SCC3/4 or SMC1)
— Allows changes during operation
— Autobaud support option
• Two SCCs (serial communication controllers)
— Ethernet/IEEE 802.3® standard optional on SCC3 and SCC4, supporting full 10-Mbps
operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Universal asynchronous receiver transmitter (UART)
— Totally transparent (bit streams)
— Totally transparent (frame-based with optional cyclic redundancy check (CRC))
• One SMC (serial management channel)
— UART
• One SPI (serial peripheral interface)
— Supports master and slave modes
— Supports multimaster operation on the same bus
• PCMCIA interface
— Master (socket) interface, release 2.1 compliant
— Supports one independent PCMCIA socket; 8-memory or I/O windows supported
• Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— Supports conditions: = ≠ < >
— Each watchpoint can generate a break point internally
• Normal high and normal low power modes to conserve power
• 1.8 V core and 3.3-V I/O operation with 5-V TTL compatibility. Refer to Table 5 for a listing of
the 5-V tolerant pins.
Figure 1 shows the MPC852T block diagram.